EBD26UB8ALFA Datasheet, PDF (6/16 Pages) Elpida Memory – 256MB Unbuffered DDR SDRAM DIMM

EBD26UB8ALFA
Byte No.
27
28
29
30
31
32
33
34
35
36 to 61
62
63
64
65 to 71
72
73 to 90
91 to 92
93 to 94
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Minimum row precharge time (tRP)
-7A
0
1
0
1
0
0
0
0
50H
-75
0 1 0 1 0 0 0 0 50H
-1A
Minimum row active to row active
delay (tRRD)
-7A
-75
0 1 0 1 0 0 0 0 50H
0 0 1 1 1 1 0 0 3CH
0 0 1 1 1 1 0 0 3CH
-1A
0 0 1 1 1 1 0 0 3CH
Minimum /RAS to /CAS delay (tRCD)
-7A
0
1
0
1
0
0
0
0
50H
-75
0 1 0 1 0 0 0 0 50H
-1A
Minimum active to precharge time
(tRAS)
-7A
-75
0 1 0 1 0 0 0 0 50H
0 0 1 0 1 1 0 1 2DH
0 0 1 0 1 1 0 1 2DH
-1A
0 0 1 1 0 0 1 0 32H
Module bank density
Address and command setup time
before clock (tIS)
-7A
-75
0 0 1 0 0 0 0 0 20H
1 0 0 1 0 0 0 0 90H
1 0 0 1 0 0 0 0 90H
-1A
1 0 1 1 0 0 0 0 B0H
Address and command hold time after
clock (tIH)
1 0 0 1 0 0 0 0 90H
-7A
-75
1 0 0 1 0 0 0 0 90H
-1A
Data input setup time before clock
(tDS)
-7A
-75
1 0 1 1 0 0 0 0 B0H
0 1 0 1 0 0 0 0 50H
0 1 0 1 0 0 0 0 50H
-1A
0 1 1 0 0 0 0 0 60H
Data input hold time after clock (tDH)
-7A
0
1
0
1
0
0
0
0
50H
-75
0 1 0 1 0 0 0 0 50H
-1A
0 1 1 0 0 0 0 0 60H
Superset information
0 0 0 0 0 0 0 0 00H
SPD Revision
Checksum for bytes 0 to 62
-7A
-75
0 0 0 0 0 0 0 0 00H
0 1 1 1 0 0 1 0 72H
1 0 0 1 1 1 0 1 9DH
-1A
0 1 0 0 0 0 1 1 43H
Manufacturer’s JEDEC ID code
1 1 1 1 1 1 1 0 FEH
Manufacturer’s JEDEC ID code
0 0 0 0 0 0 0 0 00H
Manufacturing location
Manufacturer’s part number
Revision code
Manufacturing date
Comments
20ns
20ns
20ns
15ns
15ns
15ns
20ns
20ns
20ns
45ns
45ns
50ns
128M bytes
0.9ns
0.9ns
1.1ns
0.9ns
0.9ns
1.1ns
0.5ns
0.5ns
0.6ns
0.5ns
0.5ns
0.6ns
Elpida Memory
Preliminary Data Sheet E0215E10 (Ver. 1.0)
6