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EBD11UD8ADFB Datasheet, PDF (6/19 Pages) Elpida Memory – 1GB Unbuffered DDR SDRAM DIMM (128M words x64 bits, 2 Ranks)
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EBD11UD8ADFB
Byte No.
28
29
30
31
32
33
34
35
36 to 40
41
42
43
44
45
46 to 61
62
63
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Minimum row active to row active
delay (tRRD)
-6B
0 0 1 1 0 0 0 0 30H
-7A, -7B
0 0 1 1 1 1 0 0 3CH
Minimum /RAS to /CAS delay (tRCD)
-6B
0
1
0
0
1
0
0
0
48H
-7A, -7B
0 1 0 1 0 0 0 0 50H
Minimum active to precharge time
(tRAS)
-6B
0 0 1 0 1 0 1 0 2AH
-7A, -7B
0 0 1 0 1 1 0 1 2DH
Module rank density
1 0 0 0 0 0 0 0 80H
Address and command setup time
before clock (tIS)
-6B
0 1 1 1 0 1 0 1 75H
-7A, -7B
1 0 0 1 0 0 0 0 90H
Address and command hold time after
clock (tIH)
0 1 1 1 0 1 0 1 75H
-6B
-7A, -7B
1 0 0 1 0 0 0 0 90H
Data input setup time before clock
(tDS)
-6B
0 1 0 0 0 1 0 1 45H
-7A, -7B
0 1 0 1 0 0 0 0 50H
Data input hold time after clock (tDH)
-6B
0
1
0
0
0
1
0
1
45H
-7A, -7B
0 1 0 1 0 0 0 0 50H
Superset information
0 0 0 0 0 0 0 0 00H
Active command period (tRC)
-6B
0 0 1 1 1 1 0 0 3CH
-7A, -7B
0 1 0 0 0 0 0 1 41H
Auto refresh to active/
Auto refresh command cycle (tRFC) 0 1 0 0 1 0 0 0 48H
-6B
-7A, -7B
0 1 0 0 1 0 1 1 4BH
SDRAM tCK cycle max. (tCK max.) 0 0 1 1 0 0 0 0 30H
Dout to DQS skew
-6B
0 0 1 0 1 1 0 1 2DH
-7A, -7B
0 0 1 1 0 0 1 0 32H
Data hold skew (tQHS)
-6B
0 1 0 1 0 1 0 1 55H
-7A, -7B
0 1 1 1 0 1 0 1 75H
Superset information
0 0 0 0 0 0 0 0 00H
SPD Revision
Checksum for bytes 0 to 62
-6B
-7A
0 0 0 0 0 0 0 0 00H
0 1 0 0 0 0 1 0 42H
1 1 1 1 1 0 0 1 F9H
-7B
0 0 1 0 0 1 0 0 24H
64 to 65 Manufacturer’s JEDEC ID code
0 1 1 1 1 1 1 1 7FH
Comments
12ns
15ns
18ns
20ns
42ns
45ns
512M bytes
0.75ns*1
0.9ns*1
0.75ns*1
0.9ns*1
0.45ns*1
0.5ns*1
0.45ns*1
0.5ns*1
Future use
60ns*1
65ns*1
72ns*1
75ns*1
12ns*1
450ps*1
500ps*1
550ps*1
750ps*1
Future use
Continuation
code
Data Sheet E0414E20 (Ver. 2.0)
6
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