EDE1104ABSE Datasheet, PDF (55/82 Pages) Elpida Memory – 1G bits DDR2 SDRAM

EDE1104ABSE, EDE1108ABSE, EDE1116ABSE
Burst Read Command [READ]
The Burst Read command is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising
edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start
of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency
(RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus.
The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out
appears on the DQ pin in phase with the DQS signal in a source synchronous manner.
The RL is equal to an additive latency (AL) plus /CAS latency (CL). The CL is defined by the mode register set
(MRS), similar to the existing SDR and DDR-I SDRAMs. The AL is defined by the extended mode register set
(EMRS).
T0
T1
T2
T3
T4
T5
T6
T7
T8
/CK
CK
Command READ
DQS, /DQS
DQ
CL = 3
RL = 3
NOP
≤ tDQSCK
out0 out1 out2 out3
Burst Read Operation (RL = 3, BL = 4 (AL = 0 and CL = 3))
T0
T1
T2
T3
T4
T5
T6
T7
T8
/CK
CK
Command READ
DQS, /DQS
DQ
CL = 3
RL = 3
≤ tDQSCK
NOP
out0 out1 out2 out3 out4 out5 out6 out7
Burst Read Operation (RL = 3, BL = 8 (AL = 0 and CL = 3))
Data Sheet E0852E50 (Ver. 5.0)
55