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EBE20AE4ABFA Datasheet, PDF (5/27 Pages) Elpida Memory – 2GB Registered DDR2 SDRAM DIMM
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EBE20AE4ABFA
Serial PD Matrix
Byte No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
00
Total number of bytes in serial PD
device
0
0
0
0
1
0
00
Memory type
0 0 0 0 1 0 00
Number of row address
0 0 0 0 1 1 10
Number of column address
0 0 0 0 1 0 11
Number of DIMM ranks
0 1 1 0 0 0 00
Module data width
0 1 0 0 1 0 00
Module data width continuation 0 0 0 0 0 0 0 0
Voltage interface level of this
assembly
0 0 0 0 0 1 01
DDR SDRAM cycle time, CL = 5 0 0 1 1 0 0 0 0
SDRAM access from clock (tAC) 0 1 0 0 0 1 0 1
DIMM configuration type
0 0 0 0 0 1 10
Refresh rate/type
1 0 0 0 0 0 10
Primary SDRAM width
0 0 0 0 0 1 00
Error checking SDRAM width
0 0 0 0 0 1 00
Reserved
0 0 0 0 0 0 00
SDRAM device attributes:
Burst length supported
0 0 0 0 1 1 00
SDRAM device attributes: Number
of banks on SDRAM device
0
0
0
0
1
0
00
SDRAM device attributes:
/CAS latency
0 0 1 1 1 0 00
DIMM Mechanical Characteristics 0 0 0 0 0 0 0 1
DIMM type information
0 0 0 0 0 0 01
SDRAM module attributes
0 0 0 0 0 0 00
SDRAM device attributes: General 0 0 0 0 0 0 1 1
Minimum clock cycle time at CL = 4 0 0 1 1 1 1 0 1
Maximum data access time (tAC)
from clock at CL = 4
0
1
0
1
0
0
00
Minimum clock cycle time at CL = 3 0 1 0 1 0 0 0 0
Maximum data access time (tAC)
from clock at CL = 3
0
1
1
0
0
0
00
Minimum row precharge time (tRP) 0 0 1 1 1 1 0 0
Minimum row active to row active
delay (tRRD)
0
0
0
1
1
1
10
Minimum /RAS to /CAS delay
(tRCD)
0 0 1 1 1 1 00
Minimum active to precharge time
(tRAS)
0
0
1
0
1
1
01
Module rank density
0 0 0 0 0 0 10
Address and command setup time
before clock (tIS)
0
0
1
0
0
0
00
Address and command hold time
after clock (tIH)
0
0
1
0
0
1
11
Data input setup time before clock
(tDS)
0
0
0
1
0
0
00
Hex value Comments
80H
128 bytes
08H
08H
0EH
0BH
60H
48H
00H
05H
30H
45H
06H
82H
04H
04H
00H
0CH
256 bytes
DDR2 SDRAM
14
11
1
72
0
SSTL 1.8V
3.0ns*1
0.45ns*1
ECC, Address/
Command Parity
7.8µs
×4
×4
0
4,8
08H
8
38H
01H
01H
00H
03H
3DH
50H
50H
60H
3CH
1EH
3, 4, 5
4.00mm max.
Registered
Normal
Weak Driver
50Ω ODT Support
3.75ns*1
0.5ns*1
5.0ns*1
0.6ns*1
15ns
7.5ns
3CH
15ns
2DH
02H
20H
27H
10H
45ns
2GB
0.20ns*1
0.27ns*1
0.10ns*1
Data Sheet E0875E30 (Ver. 3.0)
5
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