EDS1232AATA Datasheet, PDF (47/53 Pages) Elpida Memory – 128M bits SDRAM

EDS1232AATA
Read/Burst Write Cycle
CLK
CKE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
/CS
/RAS
/CAS
/WE
BS
Address
DQM
EDQ (input)
DQ (output)
CKE
O/CS
/RAS
/CAS
L^/WE
R:a
Bank 0
Active
VIH
C:a
Bank 0
Read
R:b
a
Bank 3
Active
a+1 a+2 a+3
Clock
suspend
C:a'
a a+1 a+2 a+3
Bank 0
Write
Bank 0
Precharge
Bank 3
Precharge
BS
Address
DQM
DQ (input)
DQ (output)
R:a
Bank 0
Active
Pr _{Auto Refresh Cycle}
C:a
R:b
Bank 0
Read
a a+1
Bank 3
Active
C:a
a+3
a a+1 a+2 a+3
Bank 0
Write
Bank 0
Precharge
Read/Burst write
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
o _CLK
CKE
/CS
d _/RAS
/CAS
/WE
u _BS
Address
DQM
DQ (input)
ct _{DQ (output)}
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VIH
A10=1
Precharge
If needed
t RP
Auto Refresh
t RC
High-Z
Auto Refresh
t RC
R:a
C:a
Active
Bank 0
a a+1
Read ^{Refresh cycle and}
Bank 0 Read cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
= VIH or VIL
Data Sheet E0386E60 (Ver. 6.0)
47