EDE5104GBSA Datasheet, PDF (43/56 Pages) Elpida Memory – 512M bits DDR-II SDRAM

EDE5104GBSA, EDE5108GBSA, EDE5116GBSA
Write data mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR-II SDRAMs, Consistent with the
implementation on DDR-I SDRAMs. It has identical timings on write operations as the data bits, and though used in
a uni-directional manner, is internally loaded identically to data bits to insure matched system timing. DM is not used
during read cycles.
T1
T2
T3
T4
T5
T6
DQS
/DQS
DQ
in in
in in
in in in in
DM
Write mask latency = 0
Data Mask Timing
[tDQSS(min.)]
/CK
CK
Command
WRIT
tWR
NOP
DQS, /DQS
tDQSS
DQ
in0
in2 in3
DM
[tDQSS(max.)]
DQS, /DQS
DQ
DM
tDQSS
in0
in2 in3
Data Mask Function, WL = 3, AL = 0 shown
Preliminary Data Sheet E0249E30 (Ver. 3.0)
43