EDS1232JCBH-6B Datasheet, PDF (42/50 Pages) Elpida Memory – 128M bits SDRAM

EDS1232JCBH-6B
Write Cycle
tCK
tCH tCL
CLK
tRC
VIH
CKE
tRAS
tRP
tRCD
/CS
/RAS
E /CAS
/WE
OBS
A10
L^Address
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
tSI tHI
DQM
DQ (input)
DQ (output)
Bank 0
Active
Mode Register Set Cycle
0 12
CLK
CKE ^VIH
/CS
/RAS
/CAS
/WE
BS
Address
valid
DQM
DQ (output)
DQ (input)
lRP
tSI
tHI
tSI t HI tSI tHI tSI tHI tSI tHI
tDPL
P_{Bank 0}
Write
Bank 0
Precharge
CL = 2
BL = 4
Bank 0 access
= VIH or VIL
r_{3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19}
odu _code
R: b
C: b
C: b’
ct _lMRD
lRCD
b
High-Z
Output mask
b+3 b’ b’+1 b’+2 b’+3
lRCD = 3
Precharge
If needed
Mode
register
Set
Bank 3
Active
Bank 3
Read
/CAS latency = 3
Burst length = 4
= VIH or VIL
Preliminary Data Sheet E0748E20 (Ver. 2.0)
42