EDS2732CABJ Datasheet, PDF (41/48 Pages) Elpida Memory – 256M bits SDRAM

EDS2732CABJ
Read Cycle/Write Cycle
CLK
CKE
/CS
/RAS
/CAS
0
VIH
123
456
78
9 10 11 12 13 14 15 16 17 18 19 20
Read cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
/WE
BS
Address
DQM
DQ (output)
DQ (input)
E CKE
/CS
/RAS
/CAS
O^/WE
BS
Address
DQM
DQ (output)
L^{DQ (input)}
R:a
Bank 0
Active
VIH
R:a
C:a
R:b
C:b
C:b'
C:b"
Bank 0
Read
a
Bank 3
Active
a+1 a+2 a+3
b
High-Z
Bank 3 Bank 0
Read Precharge
b+1 b+2 b+3 b'
Bank 3
Read
Bank 3
Read
b'+1 b" b"+1 b"+2 b"+3
Bank 3
Precharge
Write cycle
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
C:a
R:b
a a+1 a+2 a+3
C:b
C:b'
C:b"
High-Z
b b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3
Bank 0
Active
Read/Single Write Cycle
CLK
CKE
/CS
/RAS
0
VIH
/CAS
/WE
BS
Address
DQM
DQ (input)
DQ (output)
CKE
R:a
Bank 0
Active
VIH
/CS
/RAS
/CAS
/WE
BS
Address
R:a
DQM
DQ (input)
DQ (output)
Bank 0
Bank 0
Write
Bank 3
Active
Bank 3
Write
Bank 0
Precharge
Bank 3
Write
Bank 3
Write
Bank 3
Precharge
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pr_C:a
R:b
C:a' C:a
o _{Bank 0}
Read
a
Bank 3
Active
a+1 a+2 a+3
a
Bank 0 Bank 0
Write Read
a a+1 a+2 a+3
Bank 0
Precharge
Bank 3
Precharge
du _C:a
R:b
ct _{Bank 0}
a
Bank 3
a+1
C:a
C:b C:c
a+3
a
Bank 0
bc
Bank 0 Bank 0
Bank 0
Active
Read
Active
Write
Write Write
Precharge
Read/Single write
/RAS-/CAS delay = 3
/CAS latency = 3
Burst length = 4
= VIH or VIL
Data Sheet E0462E30 (Ver. 3.0)
41