EBE42FE8ACWR Datasheet, PDF (4/22 Pages) Elpida Memory – 4GB Fully Buffered DIMM

EBE42FE8ACWR
Advanced Memory Buffer Block Diagram
Southbound
Data in ^10×2
Southbound
10×2 _{Data out}
Reference
clock
1×2
/RESET
SMBus
Data merge
PLL
RE-time
Re-synch
Reset
control
Demux
10×12
PISO
10×12
Thermal
sensor
Command
decoder &
CRC check
Core
controller
and CSRs
failover
Link init SM
and control
and CSRs
Init
patterns
IBIST-RX
IBIST-TX
LAI logic
DRAM Command
Write data
FIFO
DDR state controller
and CSRs
External MemBIST
DDR calibration
Mux
4
DRAM clock
4
DRAM clock
Command
out
Mux
Mux ^{Data out}
DRAM
interface
24 _DRAM
address and
command copy1
24
DRAM
address and
command copy2
A2 for the ECC DRAMs
4 ^{A6 for the ECC DRAMs}
DRAM chip select
Data in
72+18×2
DRAM
data and strobes
Data CRC
generator and
Read FIFO
LAI
controller
Mux
Sync & idle
pattern
generator
NB LAI Buffer
IBIST-TX
IBIST-RX
Link init SM
and control
and CSRs
SMBus
controller
failover
14×6×2
PISO
14×12
Re-synch
Demux
Data merge
RE-time
Northbound _14×2
Data Out
14×2 ^Northbound
Data In
Note: This figure is a conceptual block diagram of the AMB’s data flow and clock domains.
Data Sheet E1386E10 (Ver. 1.0)
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