EDS1232CATA Datasheet, PDF (39/53 Pages) Elpida Memory – 128M bits SDRAM

EDS1232CATA
Write command to Precharge command interval (same bank)
When the precharge command is executed for the same bank as the write command that preceded it, the minimum
interval between the two commands is 1 clock. However, if the burst write operation is unfinished, the input data
must be masked by means of DQM for assurance of the clock defined by tDPL.
CLK
Command
DQM
DQ
E _CLK
Command
O_DQM
L^DQ
WRIT
tDPL
WRIT
in A0
PRE/PALL
in A1
PRE/PALL
tDPL
WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To stop write operation))
CLK
P _Command
DQM
WRIT
PRE/PALL
r _DQ
in A0
in A1
in A2
in A3
o_tDPL
duct ^{WRITE to PRECHARGE Command Interval (same bank) (BL = 4 (To write all data))}
Data Sheet E0388E11 (Ver. 1.1)
39