ECS1232JCCN-A Datasheet, PDF (38/48 Pages) Elpida Memory – 128M bits SDRAM Bare Chip

ECS1232JCCN-A
Bank active command interval
1. Same bank: The interval between the two bank active commands must be no less than tRC.
2. In the case of different bank active commands: The interval between the two bank active commands must be no
less than tRRD.
CLK
Command
Address
BS
ACT
ROW
E Bank0
Active
tRC
Bank Active to Bank Active for Same Bank
O _CLK
L^Command
ACT
ACT
ACT
ROW
Bank 0
Active
Address
ROW:0
ROW:1
BS
tRRD
PBank 0
Active
Bank 3
Active
Bank Active to Bank Active for Different Bank
Mode register set to Bank active command interval
r The interval between setting the mode register and executing a bank active command must be no less than lMRD.
CLK
o _Command
MRS
EMRS
ACT
d ^Address
OPCODE
OPCODE
BS & ROW
Mode
u ^{Register Set}
lMRD
lMRD
if needed
Extended Mode
Register Set
Bank
Active
ct ^{Mode register set to Bank active command interval}
Preliminary Data Sheet E0779E20 (Ver. 2.0)
38