EDS1232AATA-TI Datasheet, PDF (37/53 Pages) Elpida Memory – 128M bits SDRAM WTR (Wide Temperature Range)

EDS1232AATA-TI
Read with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is executed.
However, DQM must be set High so that the output buffer becomes High-Z before data input. The internal auto-
precharge of one bank starts at the next clock of the second command.
CLK
Command
BS
CL = 2
DQM
CL = 3
DQ (input)
DQ (output)
READA WRIT
in B0
in B1 in B2
High-Z
in B3
bank0 bank3
ReadA Write
Note: Internal auto-precharge starts at the timing indicated by " ".
BL = 4
Read with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
Write with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is executed.
However, in case of a burst write, data will continue to be written until one clock before the read command is
executed. The internal auto-precharge of one bank starts at 2 clocks later from the second command.
CLK
Command
BS
DQM
DQ (input)
DQ (output)
WRITA READ
in A0
out B0 out B1 out B2 out B3
bank0
WriteA
bank3
Read
CL = 3
BL = 4
Note: Internal auto-precharge starts at the timing indicated by " ".
Write with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is
necessary to separate the two commands with a bank active command.
Data Sheet E0305E30 (Ver. 3.0)
37