EDE5132BABG Datasheet, PDF (34/74 Pages) Elpida Memory – 512M bits DDR2 SDRAM

EDE5132BABG
8. The minimum delay from the read, write and precharge command to the precharge command to the same
bank is summarized below.
[Precharge and Auto Precharge Clarification]
From command To command
Minimum delay between “From
command” to “To command“
Units
Notes
Read
Precharge (to same bank as read)
AL + (BL/2) + Max.(RTP, 2) − 2
tCK
a, b
Precharge all
AL + (BL/2) + Max.(RTP, 2) − 2
Read w/AP
Precharge (to same bank as read w/AP) AL + (BL/2) + Max.(RTP, 2) − 2
Precharge all
AL + (BL/2) + Max.(RTP, 2) − 2
Write
Precharge (to same bank as write)
WL + (BL/2) + tWR
Precharge all
WL + (BL/2) + tWR
Write w/AP
Precharge (to same bank as write w/AP) WL + (BL/2) + WR
E _{Precharge all}
WL + (BL/2) + WR
Precharge
Precharge (to same bank as precharge) 1
Precharge all
1
O_{Precharge all}
Precharge
1
Precharge all
1
a. RTP[cycles] = RU{ tRTP[ns] / tCK[ns] }, where RU stands for round up.
L^{tCK(avg) should be used in place of tCK for DDR2-667/800.}
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
a, b
a, b
a, b
b
b
b
b
b
b
b
b
b. For a given bank, the precharge period should be counted from the latest precharge command, either one
bank precharge or precharge all, issued to that bank. The precharge period is satisfied after tRP
Product ^{depending on the latest precharge command issued to that bank.}
Preliminary Data Sheet E1372E10 (Ver. 1.0)
34