EDD5104ADTA Datasheet, PDF (32/49 Pages) Elpida Memory – 512M bits DDR SDRAM

EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
A Write command to the consecutive Read command interval: To complete the burst operation
Destination row of the consecutive read
command
Bank
address
Row address State
Operation
1. Same
Same
ACTIVE
To complete the burst operation, the consecutive read command should be
performed tWRD (= BL/ 2 + 2) after the write command.
2. Same
Different
—
Precharge the bank tWRD after the preceding write command. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
3. Different
Any
ACTIVE
To complete a burst operation, the consecutive read command should be
performed tWRD (= BL/ 2 + 2) after the write command.
IDLE
Precharge the bank independently of the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCD after the ACT command, the
consecutive read command can be issued.
t0
t1
t2
t3
t4
t5
t6
CK
/CK
Command
WRIT
DM
NOP
tWRD (min)
BL/2 + 2 cycle
READ
tWTR*
NOP
DQ
DQS
in0 in1 in2 in3
out0 out1 out2
INPUT
OUTPUT
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
WRITE to READ Command Interval
BL = 4
CL = 2
Data Sheet E0384E30 (Ver. 3.0)
32