EDS2532AABH-1AR2 Datasheet, PDF (31/48 Pages) Elpida Memory – 256M bits SDRAM

EDS2532AABH-1AR2
Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the same
bank as the preceding write command, the read command can be performed after an interval of no less than 1
clock. However, in the case of a burst write, data will continue to be written until one clock before the read
command is executed.
CLK
Command
DQM
DQ (input)
E_{DQ (output)}
OL_CLK
WRIT READ
in A0
out B0 out B1
Column = A
Write _{Column = B}
Read
/CAS Latency
Column = B
Dout
WRITE to READ Command Interval (1)
out B2
out B3
Burst Write Mode
CL = 2
BL = 4
Bank 0
Command
DQM
WRIT
READ
DQ (input)
in A0
in A1
P DQ (output)
out B0 out B1 out B2 out B3
Column = A
Write
Column = B
Read
/CAS Latency
Column = B
Dout
r_{WRITE to READ Command Interval (2)}
Burst Write Mode
CL = 2
BL = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be
o executed; it is necessary to separate the two commands with a precharge command and a bank active
command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1
clock, provided that the other bank is in the bank active state. However, in the case of a burst write, data will
d ^{continue to be written until one clock before the read command is executed (as in the case of the same bank and}
uct ^{the same address).}
Data Sheet E0517E20 (Ver. 2.0)
31