EDS1232AABB Datasheet, PDF (30/55 Pages) Elpida Memory – 128M bits SDRAM

EDS1232AABB, EDS1232AATA
Auto Precharge
Read with auto-precharge
In this operation, since precharge is automatically performed after completing a read operation, a precharge
command need not be executed after each read operation. The command executed for the same bank after the
execution of this command must be the bank active (ACT) command. In addition, an interval defined by lAPR is
required before execution of the next command.
[Clock cycle time]
/CAS latency
Precharge start cycle
3
2 cycle before the final data is output
2
1 cycle before the final data is output
CLK
CL=2 Command
DQ
ACT
CL=3 Command
DQ
ACT
READA
lRAS
READA
lRAS
ACT
out0
out1
out2
out3
lAPR
ACT
out0
out1
out2
out3
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of tRAS (lRAS) is required between previous active (ACT) command and internal precharge " ".
lAPR
Burst Read (BL = 4)
Write with auto-precharge
In this operation, since precharge is automatically performed after completing a burst write or single write operation,
a precharge command need not be executed after each write operation. The command executed for the same bank
after the execution of this command must be the bank active (ACT) command. In addition, an interval of lDAL is
required between the final valid data input and input of next command.
CLK
Command ACT
WRITA
I_RAS
ACT
DQ
in0 in1 in2 in3
lDAL
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACT) command
and internal precharge " ".
Burst Write (BL = 4)
Preliminary Data Sheet E0205E50 (Ver. 5.0)
30