ECS2532EECN-A Datasheet, PDF (30/48 Pages) Elpida Memory – 256M bits SDRAM Bare Chip

ECS2532EECN-A
Command Intervals
Read command to Read command interval
1. Same bank, same ROW address: When another read command is executed at the same ROW address of the
same bank as the preceding read command execution, the second read can be performed after an interval of no
less than 1 clock. Even when the first command is a burst read that is not yet finished, the data read by the
second command will be valid.
CLK
Command
ACT
READ READ
Address
Row
Column A Column B
BS
E _DQ
out A0 out B0 out B1 out B2 out B3
Bank0
Active
Column =A Column =B Column =A Column =B
Read
Read
Dout
Dout
O^{READ to READ Command Interval (same ROW address in same bank)}
CL = 3
BL = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read
commands cannot be executed; it is necessary to separate the two read commands with a precharge command
and a bank active command.
L ^{3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1}
clock, provided that the other bank is in the bank active state. Even when the first command is a burst read that
is not yet finished, the data read by the second command will be valid.
CLK
Command
ACT
ACT READ READ
P ^Address
Row 0
Row 1 Column A Column B
BS
DQ
r ^Bank0
oduct ^Active
out A0 out B0 out B1 out B2 out B3
Bank3 Bank0 Bank3
Active Read Read
Bank0 Bank3
Dout Dout
READ to READ Command Interval (different bank)
CL = 3
BL = 4
Data Sheet E0697E50 (Ver. 5.0)
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