EDJ2104EDBG Datasheet, PDF (3/150 Pages) Elpida Memory – ZQ calibration for DQ drive and ODT

EDJ2104EDBG, EDJ2108EDBG
Pin Configurations
/xxx indicates active low signal.
78-ball FBGA (×4 configuration)
1
2
3
A
VSS VDD NC
B
VSS VSSQ DQ0
C
VDDQ DQ2 DQS
D
VSSQ NC /DQS
E
VREFDQ VDDQ NC
F
NC VSS /RAS
G
ODT VDD /CAS
H
NC /CS /WE
J
VSS BA0 BA2
K
VDD A3 A0
L
VSS A5 A2
M
VDD A7 A9
N
VSS /RESET A13
7
8
9
NC VSS VDD
DM VSSQ VDDQ
DQ1 DQ3 VSSQ
VDD VSS VSSQ
NC NC VDDQ
CK VSS NC
/CK VDD CKE
A10(AP) ZQ NC
NC VREFCA VSS
A12(/BC) BA1 VDD
A1 A4 VSS
A11 A6 VDD
A14 A8 VSS
(Top view)
78-ball FBGA (×8 configuration)
1
2
3
A
VSS VDD NC
B
VSS VSSQ DQ0
C
VDDQ DQ2 DQS
D
VSSQ DQ6 /DQS
E
VREFDQ VDDQ ^DQ4
F
NC VSS /RAS
G
ODT VDD /CAS
H
NC /CS /WE
J
VSS BA0 BA2
K
VDD A3 A0
L
VSS A5 A2
M
VDD A7 A9
N
VSS /RESET A13
7
8
9
NU/(/TDQS) VSS VDD
DM/TDQS VSSQ VDDQ
DQ1 DQ3 VSSQ
VDD VSS VSSQ
DQ7 DQ5 _VDDQ
CK VSS NC
/CK VDD CKE
A10(AP) ZQ NC
NC VREFCA VSS
A12(/BC) BA1 VDD
A1 A4 VSS
A11 A6 VDD
A14 A8 VSS
(Top view)
Pin name
Function
Pin name
Function
A0 to A14*³
BA0 to BA2*³
Address inputs
A10 (AP): Auto precharge
A12(/BC): Burst chop
Bank select
/RESET*³
VDD
Active low asynchronous reset
Supply voltage for internal circuit
DQ0 to DQ7
Data input/output
VSS
Ground for internal circuit
DQS, /DQS
Differential data strobe
VDDQ
Supply voltage for DQ circuit
TDQS, /TDQS
/CS*³
/RAS, /CAS, /WE*³
CKE*³
CK, /CK
DM
ODT*³
Termination data strobe
Chip select
Command input
Clock enable
Differential clock input
Write data mask
ODT control
VSSQ
VREFDQ
VREFCA
ZQ
NC*¹
NU*²
Ground for DQ circuit
Reference voltage for DQ
Reference voltage
Reference pin for ZQ calibration
No connection
Not usable
Notes: 1. Not internally connected with die.
2. Don’t connect. Internally connected.
3. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Data Sheet E1797E41 (Ver. 4.1)
3