EDL6416CBBH Datasheet, PDF (29/59 Pages) Elpida Memory – 64M bits Mobile RAM™

EDL6416CBBH
Write to Read Command Interval
Write command and Read command interval is also 1 cycle. Only the write data before Read command will be
written. The data bus must be High-Z at least one cycle prior to the first DOUT.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
/CAS latency = 2
Command
DQ
WRITE A READ B
Hi-Z
DA1
QB1
QB2
QB3
QB4
/CAS latency = 3
Command
DQ
WRITE A READ B
Hi-Z
DA1
QB1
QB2
QB3
QB4
Write to Read Command Interval
Preliminary Data Sheet E1138E21 (Ver. 2.1)
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