ECS2516ADCN-A Datasheet, PDF (29/48 Pages) Elpida Memory – 256M bits SDRAM Bare Chip

ECS2516ADCN-A
Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to High-Z after the /CAS latency from the burst stop command.
CLK
Command
READ
BST
DQ
(CL = 2)
out
out
out
High-Z
DQ
E^{(CL = 3)}
High-Z
out
out
out
Burst Stop at Read
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
to High-Z at the same clock with the burst stop command.
O_CLK
Command
L _Product DQ
WRITE
BST
in
in
in
in
Burst Stop at Write
High-Z
Preliminary Data Sheet E0661E20 (Ver. 2.0)
29