HM5264165F-75 Datasheet, PDF (28/65 Pages) Hitachi Semiconductor – 64M LVTTL interface SDRAM 133 MHz/100 MHz

HM5264165F/HM5264805F/HM5264405F-75/A60/B60
Command Intervals
Read command to Read command interval:
1. Same bank, same ROW address: When another read command is executed at the same ROW address
of the same bank as the preceding read command execution, the second read can be performed after an
interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data
read by the second command will be valid.
READ to READ Command Interval (same ROW address in same bank)
CLK
Command
Address
BS
Dout
ACTV
Row
READ READ
Column A Column B
Bank0
Active
out A0 out B0 out B1 out B2 out B3
Column =A Column =B Column =A Column =B
Read
Read
Dout
Dout
CAS Latency = 3
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read
commands cannot be executed; it is necessary to separate the two read commands with a precharge command
and a bank-active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. Even when the first command is a burst
read that is not yet finished, the data read by the second command will be valid.
READ to READ Command Interval (different bank)
CLK
Command
Address
BS
Dout
ACTV
Row 0
Bank0
Active
ACTV READ READ
Row 1 Column A Column B
Bank3 Bank0 Bank3
Active Read Read
out A0 out B0 out B1 out B2 out B3
Bank0 Bank3
Dout Dout
CAS Latency = 3
Burst Length = 4
Data Sheet E0135H10
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