EDD2508AMTA Datasheet, PDF (28/34 Pages) Elpida Memory – 256M bits DDR SDRAM

EDD2508AMTA, EDD2516AMTA
Mode Register Set Cycle
/CK
CK
CKE
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
VIH
/CS
/RAS
/CAS
/WE
E _BA
code
Address
valid
code
R: b
O_DM
DQS
L DQ (output)
High-Z
High-Z
tRP
tMRD
Precharge
If needed
Mode
register
set
Bank 3
Active
P Read/Write Cycle
0 12345 6
/CK
CK
r ^{CKE VIH}
/CS
o _/RAS
/CAS
/WE
d ^BA
Address
R:a
DM
C:a R:b
u _DQS
DQ (output)
DQ (input)
High-Z
a
tRWD
c _{Bank 0}
t ^Active
Bank 0 Bank 3
Read Active
C: b
b
Bank 3
Read
Bank 3
Precharge
CL = 2
BL = 4
= VIH or VIL
7 8 9 10 11 12 13 14 15
C:b
C:b''
b
Bank 3
Write
tWRD
b’’
Bank 3
Read Read cycle
CL = 2
BL = 4
=VIH or VIL
Preliminary Data Sheet E0405E10 (Ver. 1.0)
28