EDS2532CASG Datasheet, PDF (27/48 Pages) Elpida Memory – 256M bits SDRAM

EDS2532CASG
Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to High-Z after the /CAS latency from the burst stop command.
CLK
Command
READ
BST
DQ
(CL = 2)
out
out
out
High-Z
E DQ
(CL = 3)
High-Z
out
out
out
Burst Stop at Read
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
O^{to High-Z at the same clock with the burst stop command.}
CLK
L ^Command
WRITE
BST
DQ
in
in
in
in
Product ^{Burst Stop at Write}
High-Z
Data Sheet E0541E21 (Ver. 2.1)
27