EDS2532EEBH-9A Datasheet, PDF (25/50 Pages) Elpida Memory – 256M bits SDRAM (8M words x 32 bits)

EDS2532EEBH-9A
Operation of the SDRAM
Read/Write Operations
Bank active
Before executing a read or write operation, the corresponding bank and the row address must be activated by the
bank active (ACT) command. An interval of tRCD is required between the bank active command input and the
following read/write command input.
Read operation
A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1)
cycle after read command set. The SDRAM can perform a burst read operation.
The burst length can be set to 1, 2, 4 and 8. The start address for a burst read is specified by the column address
and the bank select address at the read command set cycle. In a read operation, data output starts after the number
of clocks specified by the /CAS Latency. The /CAS Latency can be set to 2 or 3.
When the burst length is 1, 2, 4 and 8 the DOUT buffer automatically becomes High-Z at the next clock after the
successive burst-length data has been output.
The /CAS latency and burst length must be specified at the mode register.
CLK
Command
tRCD
ACT
READ
Address
Row
Column
CL = 2
DQ
CL = 3
out 0 out 1 out 2 out 3
out 0 out 1 out 2 out 3
/CAS Latency
CL = /CAS latency
Burst Length = 4
CLK
Command
Address
tRCD
ACT
READ
Row
Column
BL = 1
DQ
BL = 2
BL = 4
BL = 8
out 0
out 0 out 1
out 0 out 1 out 2 out 3
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7
Burst Length
BL : Burst Length
/CAS Latency = 2
Preliminary Data Sheet E0617E40 (Ver. 4.0)
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