EDE5104AGSE Datasheet, PDF (24/65 Pages) Elpida Memory – 512M bits DDR2 SDRAM

EDE5104AGSE, EDE5108AGSE
Current state
/CS /RAS /CAS /WE Address
Command Operation
Extended Mode H
×
×
×
×
DESL
Nop -> Enter idle after tMRD
register accessing L
H
H
H
×
NOP
Nop -> Enter idle after tMRD
L
H
L
H
BA, CA, A10 (AP)
READ
ILLEGAL
L
H
L
H
BA, CA, A10 (AP)
READA
ILLEGAL
L
H
L
L
BA, CA, A10 (AP)
WRIT
ILLEGAL
L
H
L
L
BA, CA, A10 (AP)
WRITA
ILLEGAL
L
L
H
H
BA, RA
ACT
ILLEGAL
L
L
H
L
BA, A10 (AP)
PRE
ILLEGAL
L
L
H
L
A10 (AP)
PALL
ILLEGAL
L
L
L
H
×
REF
ILLEGAL
L
L
L
H
×
SELF
ILLEGAL
L
L
L
L
BA, MRS-OPCODE MRS
ILLEGAL
L
L
L
L
BA, EMRS-OPCODE EMRS
ILLEGAL
Remark: H = VIH. L = VIL. × = VIH or VIL
Notes: 1. This command may be issued for other banks, depending on the state of the banks.
2. All banks must be in "IDLE".
3. All AC timing specs must be met.
4. Only allowed at the boundary of 4 bits burst. Burst interruption at other timings are illegal.
Note
Preliminary Data Sheet E0715E20 (Ver. 2.0)
24