EDD5116AFTA-H Datasheet, PDF (24/52 Pages) Elpida Memory – 512M bits DDR SDRAM High Quality Product

EDD5116AFTA-H
Operation of the DDR SDRAM
Power-up Sequence
(1) Apply power and maintain CKE at an LVCMOS low state (all other inputs are undefined).
Apply VDD before or at the same time as VDDQ.
Apply VDDQ before or at the same time as VTT and VREF.
(2) Start clock and maintain stable condition for a minimum of 200 µs.
(3) After the minimum 200 µs of stable power and clock (CK, /CK), apply NOP and take CKE high.
(4) Issue precharge all command for the device.
(5) Issue EMRS to enable DLL.
(6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of
clock input is required to lock the DLL after every DLL reset).
(7) Issue precharge all command for the device.
(8) Issue 2 or more auto-refresh commands.
(9) Issue a mode register set command to initialize device operation with bit A8 set to low in order to avoid resetting
the DLL.
CK
/CK
Command
(4)
(5)
(6)
(7)
(8)
PALL
EMRS
MRS
PALL
RERFEF
REF
2 cycles (min.) 2 cycles (min.) 2 cycles (min.)
t_RP
t_RFC
DLL enable
DLL reset with A8 = High
200 cycles (min)
Power-up Sequence after CKE Goes High
(9)
MRS
Any
command
t_RFC
2 cycles (min.)
Disable DLL reset with A8 = Low
Preliminary Data Sheet E0957E30 (Ver. 3.0)
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