EDS2532AABH-6B Datasheet, PDF (20/48 Pages) Elpida Memory – 256M bits SDRAM (8M words x 32 bits)

EDS2532AABH-6B
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A11, BA0 and BA1) during mode register set cycles.
The mode register consists of five sections, each of which is assigned to address pins.
BA1, BA0, A8, A9, A10, A11: (OPCODE): The SDRAM has two types of write modes. One is the burst write mode,
and the other is the single write mode. These bits specify write mode.
Burst read and burst write: Burst write is performed for the specified burst length starting from the column address
specified in the write cycle.
Burst read and single write: Data is only written to the column address specified during the write cycle, regardless of
the burst length.
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the /CAS latency.
A3: (BT): A burst type is specified.
A2, A1, A0: (BL): These pins specify the burst length.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
OPCODE
0
LMODE
BT
BL
A6 A5 A4 CAS latency
000
R
A3 Burst type
0 Sequential
Burst length
A2 A1 A0
BT=0 BT=1
001
R
1 Interleave
00 0 1
1
010
2
00 1 2
2
011
3
01 0 4
4
1 XX
R
01 1 8
8
10 0 R
R
BA1 BA0 A11 A10 A9
0 00 00
0 1X X0
A8 Write mode
0 Burst read and burst write
0
R
10 1 R
R
11 0 R
R
1 1 1 F.P. R
1 0X X0 0
R
1 1X X0 0
R
X XX X0 ¹
R
F.P.: Full Page
X X X X ^{1 0 Burst read and single write} _{R is Reserved (inhibit)}
X XX X1 ¹
R
X: 0 or 1
Mode Register Set Timing
Data Sheet E0494E40 (Ver. 4.0)
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