EDX5116ABSE Datasheet, PDF (19/78 Pages) Elpida Memory – 512M bits XDR DRAM (32M words x16 bits)

EDX5116ABSE
Figure 7 ACT-, RD, WR-, PRE-to-PRE Packet Interactions
C_CF_FM_M
C^CF^FM^MN^N
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
R^RQQ¹1¹1^..0..0
ACT PRE
ab
D^DQQ¹1⁵5^..0..0 ^{No limit}
DDQQNN151.5.0..0
ACT
PRE
a
t_RAS
b
APd Case (activate-precharge different bank)
a: ROWA Packet with ACT,Ba,Ra
b: ROWP Packet with PRE,Bb
Ba # Bb
APs Case (activate-precharge same bank)
a: ROWA Packet with ACT,Ba,Ra
b: ROWP Packet with PRR,Bb
Ba = Bb
C^CFF^MM
CCFFMMNN
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
R^RQQ¹1¹1^...⁰.0
RD PRE
ab
D^DQQ¹1⁵5^...⁰.0 ^{No limit}
DDQQNN115.5.0..0
RD
PRE
a _tRDP
b
RPd Case (read-precharge different bank)
a: COL Packet with RD,Ba,Ca
b: ROWP Packet with PRE,Bb
Ba # Bb
RPs Case (read-precharge same bank)
a: COL Packet with RD,Ba,Ca
b: ROWP Packet with PRR,Bb
Ba = Bb
C^CFF^MM
CCFFMMNN
T₀ T₁ T₂ T₃ T₄ T₅ T₆ T₇ T₈ T₉ T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
R^RQQ¹1¹1^...⁰.0
WR PRE
ab
D^DQQ¹1⁵5^...⁰.0 ^{No limit}
DDQQNN115.5.0..0
WR
PRE
a
t_WRP
b
WPd Case (write-precharge different bank)
a: COL Packet with WR,Ba,Ca
b: ROWP Packet with PRE,Bb
Ba # Bb
WPs Case (write-precharge same bank)
a: COL Packet with WR,Ba,Ca
b: ROWP Packet with PRE,Bb
Ba = Bb
C_CF_FM_M
CCFFMMN N
T₀ T₁ T₂ T₃
R_RQ_Q11₁.₁.0_..0
PRE
a
t_PP
D_DQ_Q1₁5.₅.0_..0
DDQQNN151..50..0
T₄ T₅
PRE
b
T₆ T₇
PRE
a
T₈ T₉ T₁₀ T₁₁ T₁₂ T₁₃ T₁₄ T₁₅ T₁₆ T₁₇ T₁₈ T₁₉ T₂₀ T₂₁ T₂₂ T₂₃
t_RP
ACT
t_RAS
PRE
b
t_RC
b
PPd Case (precharge-precharge different bank)
a: ROWP Packet with PRE,Ba
b: ROWP Packet with PRE,Bb
Ba # Bb
PPs Case (precharge-precharge same bank)
a: ROWP Packet with PRE,Ba
b: ROWP Packet with PRE,Bb
Ba = Bb
Preliminary Data Sheet E0643E30 (Ver. 3.0)
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