EDE1108AJBG-1 Datasheet, PDF (19/74 Pages) Elpida Memory – 1G bits DDR2 SDRAM

EDE1108AJBG-1, EDE1116AJBG-1
5. tJIT (per) is defined as the largest deviation of any single tCK from tCK (avg).
tJIT (per) = Min./Max. of { tCK_j − tCK (avg) where j = 1 to 200}
tJIT (per) defines the single period jitter when the DLL is already locked. tJIT (per, lck) uses the same
definition for single period jitter, during the DLL locking period only. tJIT (per) and tJIT (per, lck) are not
subject to production test.
6. tJIT (cc) is defined as the absolute difference in clock period between two consecutive clock cycles:
tJIT (cc) = Max. of |tCK_j+1 − tCK_j|
tJIT (cc) is defines the cycle to cycle jitter when the DLL is already locked. tJIT (cc, lck) uses the same
definition for cycle to cycle jitter, during the DLL locking period only. tJIT (cc) and tJIT (cc, lck) are not
subject to production test.
7. tERR (nper) is defined as the cumulative error across multiple consecutive cycles from tCK (avg).
tERR (nper) is not subject to production test.
tERR(nper
)
=
∑ⁿ

tCKj_
−
n
×
tCK(avg))
 ^{j =1}

2 ≤ n ≤ 50 for tERR (nper)
8. These parameters are specified per their average values, however it is understood that the following
relationship between the average timing and the absolute instantaneous timing hold at all times.
(minimum and maximum of spec values are to be used for calculations in the table below.)
Parameter
Symbol min.
max.
Unit
Absolute clock period
tCK (abs) tCK (avg) min. + tJIT (per) min. tCK (avg) max. + tJIT (per) max. ps
Absolute clock high pulse
width
tCH (abs)
tCH (avg) min. × tCK (avg) min.
+ tJIT (duty) min.
tCH (avg) max. × tCK (avg) max.
+ tJIT (duty) max.
ps
Absolute clock low pulse
width
tCL (abs)
tCL (avg) min. × tCK (avg) min.
+ tJIT (duty) min.
tCL (avg) max. × tCK (avg) max.
+ tJIT (duty) max.
ps
Example: For DDR2-667, tCH(abs) min. = ( 0.48 × 3000 ps ) - 125ps = 1315ps
Data Sheet E1733E31 (Ver.3.1)
19