EBE20RE4ABFA Datasheet, PDF (19/29 Pages) Elpida Memory – 2GB Registered DDR2 SDRAM DIMM

EBE20RE4ABFA
-5C
-4A
Frequency (Mbps)
533
400
Parameter
Four active window period
/CAS to /CAS command delay
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
Internal read to precharge command delay
Exit self-refresh to a non-read command
Symbol
tFAW
tCCD
tWR
tDAL
tWTR
tRTP
tXSNR
min.
max.
37.5

2

15

WR +
RU(tRP/tCK)

7.5

7.5

tRFC + 10 
min.
max.
37.5

2

15

WR +
RU(tRP/tCK)

10

7.5

tRFC + 10 
Unit Notes
ns
tCK
ns
tCK 1, 9
ns
ns
ns
Exit self-refresh to a read command
tXSRD 200

Exit precharge power-down to any non-read
command
tXP
2

Exit active power-down to read command tXARD 2

Exit active power-down to read command
(slow exit/low power mode)
tXARDS 6 − AL

CKE minimum pulse width (high and low
pulse width)
tCKE
3

Output impedance test driver delay
tOIT
0
12
200

2

2

6 − AL

3

0
12
tCK
tCK
tCK 3
tCK 2, 3
tCK
ns
MRS command to ODT update delay
tMOD
0
12
0
12
ns
Auto-refresh
time
to
active/auto-refresh
command
tRFC
127.5

127.5

ns
Average periodic refresh interval
(0°C ≤ TC ≤ +85°C)
tREFI

7.8

7.8
µs
(+85°C < TC ≤ +95°C)
tREFI

3.9

3.9
µs
Minimum time clocks remains ON after CKE
asynchronously drops low
tDELAY
tIS + tCK +
tIH

tIS + tCK +
tIH

ns
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIL(DC) level for a rising signal and VIH(DC) for a falling signal applied to the device under test.
DQS
CK
/DQS
/CK
tDS tDH
tDS tDH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
tIS
tIH
tIS
tIH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
Data Sheet E0873E40 (Ver. 4.0)
19