UPD45128163-I Datasheet, PDF (17/86 Pages) Elpida Memory – 128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

µPD45128163-I
4.5 Command Truth Table for CKE
Current State
CKE /CS /RAS /CAS /WE Address
Action
Notes
n–1 n
Self refresh
H × × × × ××
INVALID, CLK (n – 1) would exit self refresh
L H H × × ××
Self refresh recovery
L H L H H ××
Self refresh recovery
L H L H L ××
ILLEGAL
L H L L × ××
ILLEGAL
L L × × × ××
Maintain self refresh
Self refresh recovery H H H × × × ×
Idle after tRC
H H L H H ××
Idle after tRC
H H L H L ××
ILLEGAL
H H L L × ××
ILLEGAL
H L H × × ××
ILLEGAL
H L L H H ××
ILLEGAL
H L L H L ××
ILLEGAL
H L L L × ××
ILLEGAL
Power down
H× × × × ×
INVALID, CLK (n – 1) would exit power down
L H H × × ××
EXIT power down → Idle
L H L H H H×
EXIT power down → Idle
L L × × × ××
Maintain power down mode
All banks idle
HHH× × ×
Refer to operations in Operative Command Table
HHLH× ×
Refer to operations in Operative Command Table
HHL LH ×
Refer to operations in Operative Command Table
H H L L L H×
CBR (auto) Refresh
H H L L L L Op-Code Refer to operations in Operative Command Table
HLH×× ×
Refer to operations in Operative Command Table
HLLH× ×
Refer to operations in Operative Command Table
HL L LH×
Refer to operations in Operative Command Table
H L L L L H×
Self refresh
1
H L L L L L Op-Code Refer to operations in Operative Command Table
L × × × × ××
Power down
1
Row active
H × × × × ××
Refer to operations in Operative Command Table
L × × × × ××
Power down
1
Any state other than H H × × × ×
Refer to operations in Operative Command Table
listed above
H L × × × ××
Begin clock suspend next cycle
2
L H × × × ××
Exit clock suspend next cycle
L L × × × ××
Maintain clock suspend
Notes 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all
banks idle or row active state.
2. Must be legal command as defined in Operative Command Table.
Remark H = High level, L = Low level, × = High or Low level (Don't care)
Data Sheet E0346N10 (Ver. 1.0)
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