HM51W16165 Datasheet, PDF (16/35 Pages) Hitachi Semiconductor – 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh

HM51W16165 Series, HM51W18165 Series
21. t_ASC, t_CAH, t_RCS, t_WCS, t_WCH, t_CSR and t_RPC are determined by the earlier falling edge of UCAS or LCAS.
22. t_CRP, t_CHR, t_RCH, t_CPA and t_CPW are determined by the later rising edge of UCAS or LCAS.
23. t_CWL, t_DH, t_DS and t_CHS should be satisfied by both UCAS and LCAS.
24. t_CP is determined by the time that both UCAS and LCAS are high.
25. t_HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO
page mode mix cycle (1), (2)), minimum value of CAS cycle (t_CAS + t_CP + 2 t_T) becomes greater
than the specified t_HPC (min) value.The value of CAS cycle time of mixed EDO page mode is
shown in EDO page mode mix cycle (1) and (2).
26. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large V_CC/V_SS line noise, which causes to degrade V_IH min/V_IL max level.
27. Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between t_OHR and t_OH, and between t_OFR and t_OFF.
28. Please do not use t_RASS timing, 10 µs ≤ t_RASS ≤ 100 µs. During this period, the device is in
transition state from normal operation mode to self refresh mode. If t_RASS ≥ 100 µs, then RAS
precharge time should use t_RPS instead of t_RP.
29. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR
refresh should be executed within 15.6 µs immediately after exiting from and before entering
into self refresh mode.
30. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 4096 or 1024
cycles (4096 cycles: HM51W16165 Series, 1024 cycles: HM51W18165 Series) of distributed
CBR refresh with 15.6 µs interval should be executed within 64 or 16 ms (64 ms: HM51W16165,
16 ms: HM51W18165) immediately after exiting from and before entering into the self refresh
mode.
31. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
32. XXX: H or L (H: V_IH (min) ≤ V_IN ≤ V_IH (max), L: V_IL (min) ≤ V_IN ≤ V_IL (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied V_IH or V_IL.
Data Sheet E0153H10
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