EBE11UD8AGSA Datasheet, PDF (16/22 Pages) Elpida Memory – 1GB DDR2 SDRAM SO-DIMM (128M words x 64 bits, 2 Ranks)

EBE11UD8AGSA
-6E
-5C
Frequency (Mbps)
667
533
Parameter
Symbol min.
max.
min.
max.
Unit Notes
Internal write to read command delay
tWTR
7.5

7.5

ns
Internal read to precharge command delay tRTP
7.5

7.5

ns
Exit self refresh to a non-read command tXSNR
tRFC + 10 
tRFC + 10 
ns
Exit self refresh to a read command
tXSRD 200

200

tCK
Exit precharge power down to any non-read
command
tXP
2

2

tCK
Exit active power down to read command tXARD 2

2

tCK 3
Exit active power down to read command
(slow exit/low power mode)
tXARDS
7− AL

CKE minimum pulse width (high and low
pulse width)
tCKE
3

6 − AL

3

tCK 2, 3
tCK
Output impedance test driver delay
tOIT
0
12
0
12
ns
Auto refresh to active/auto refresh
command time
Average periodic refresh interval
(0°C ≤ TC ≤ +85°C)
tRFC
105
tREFI


105
7.8


ns
7.8
µs
(+85°C < TC ≤ +95°C)
tREFI

3.9

3.9
µs
Minimum time clocks remains ON after CKE
asynchronously drops low
tDELAY
tIS + tCK +
tIH

tIS + tCK +
tIH

ns
Notes: 1. For each of the terms above, if not already an integer, round to the next higher integer.
2. AL: Additive Latency.
3. MRS A12 bit defines which active power down exit timing to be applied.
4. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test.
5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the
VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
DQS
CK
/DQS
/CK
tDS tDH
tDS tDH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
tIS
tIH
tIS
tIH
VDDQ
VIH (AC)(min.)
VIH (DC)(min.)
VREF
VIL (DC)(max.)
VIL (AC)(max.)
VSS
Input Waveform Timing 1 (tDS, tDH)
Input Waveform Timing 2 (tIS, tIH)
Data Sheet E0827E10 (Ver. 1.0)
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