EBE25UC8AAFA Datasheet, PDF (15/22 Pages) Elpida Memory – 256MB Unbuffered DDR2 SDRAM DIMM

EBE25UC8AAFA
AC Characteristics (TC = 0 to +85°C, VDD, VDDQ = 1.8V ± 0.1V, VSS = 0V)
(DDR2 SDRAM Component Specification)
-5C
-4A, -4C
Frequency (Mbps)
533
400
Parameter
Symbol min.
max.
min.
max.
Unit Notes
/CAS latency
Active to read or write command delay
Precharge command period
Active to active/auto refresh command
Etime
DQ output access time from CK, /CK
DQS output access time from CK, /CK
CK high-level width
O_{CK low-level width}
CK half period
L ^{Clock cycle time}
CL
4
tRCD 15
tRP
15
tRC
60
tAC
−500
tDQSCK −450
tCH
0.45
tCL
0.45
tHP
min.
(tCL, tCH)
tCK
3750
5



+500
+450
0.55
0.55

8000
3 (-4A)
4 (-4C)
15 (-4A)
20 (-4C)
15 (-4A)
20 (-4C)
60 (-4A)
65 (-4C)
−600
−500
0.45
0.45
min.
(tCL, tCH)
5000
5 (-4A)
5 (-4C)



+600
+500
0.55
0.55

8000
tCK
ns
ns
ns
ps
ps
tCK
tCK
ps
ps
DQ and DM input hold time
tDH
225
DQ and DM input setup time
tDS
Control and Address input pulse width
for each input
DQ and DM input pulse width for each
input
P Data-out high-impedance time from
CK,/CK
Data-out low-impedance time from
CK,/CK
tIPW
tDIPW
tHZ
tLZ
DQS-DQ skew for DQS and associated
r DQ signals
tDQSQ
DQ hold skew factor
tQHS
100
0.6
0.35

tAC min.


o ^{DQ/DQS output hold time from DQS}
Write command to first DQS latching
transition
DQS input high pulse width
tQH
tHP – tQHS
tDQSS WL − 0.25
tDQSH 0.35
d DQS input low pulse width
tDQSL 0.35
DQS falling edge to CK setup time
tDSS 0.2
DQS falling edge hold time from CK tDSH 0.2
u ^{Mode register set command cycle time tMRD 2}
Write preamble setup time
tWPRES 0
Write postamble
tWPST 0.4
Write preamble
tWPRE 0.25
c _{Address and control input hold time}
tIH
375
t ^{Address and control input setup time tIS}
250

275

150

0.6

0.35
tAC max. 
tAC max. tAC min.
300

400


tHP – tQHS
WL + 0.25 WL − 0.25

0.35

0.35

0.2

0.2

2

0
0.6
0.4

0.25

475

350




tAC max.
tAC max.
350
450

WL + 0.25






0.6



ps 5
ps 4
tCK
tCK
ps
ps
ps
ps
ps
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps 5
ps 4
Read preamble
tRPRE 0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST 0.4
0.6
0.4
0.6
tCK
Active to precharge command
tRAS 45
70000
45
70000
ns
Active to auto-precharge delay
tRAP tRCD min.

tRCD min.

ns
Preliminary Data Sheet E0465E10 (Ver. 1.0)
15