HB54R1G9F2 Datasheet, PDF (13/16 Pages) Elpida Memory – 1GB Registered DDR SDRAM DIMM

HB54R1G9F2-A75B/B75B/10B
Pin Capacitance (TA = 25°C, VCC, VCCQ = 2.5V ± 0.2V)
Parameter
Symbol
Pins
max.
Unit
Notes
Input capacitance
CI1
Address, /RAS, /CAS, /WE,
/S, CKE
10
pF
1, 3
Input capacitance
CI2
CK, /CK
20
pF
1, 3
Data and DQS input/output
capacitance
CO
DQ, DQS, CB, DM
20
pF
1, 2, 3
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VCCQ/2, ∆VOUT = 0.2V.
2. Dout circuits are disabled.
3. This parameter is sampled and not 100% tested.
Timing Parameter Measured in Clock Cycle for Registered DIMM
Parameter
Write to pre-charge command delay (same bank)
Read to pre-charge command delay (same bank)
Write to read command delay (to input all data)
Burst stop command to write command delay
(CL = 3)
(CL = 3.5)
Burst stop command to DQ High-Z
(CL = 3)
(CL = 3.5)
Read command to write command delay (to output all data)
(CL = 3)
(CL = 3.5)
Pre-charge command to High-Z
(CL = 3)
(CL = 3.5)
Write command to data in latency
Write recovery
Register set command to active or register set command
Self refresh exit to non-read command
Self refresh exit to read command
Power down entry
Power down exit to command input
CKE minimum pulse width
Symbol
tWPD
tRPD
tWRD
tBSTW
tBSTW
tBSTZ
tBSTZ
tRWD
tRWD
tHZP
tHZP
tWCD
tWR
tMRD
tSNR
tSRD
tPDEN
tPDEX
tCKEPW
Number of clock cycle
min.
max.
3 + BL/2
BL/2
2 + BL/2
2
3
3
3.5
2 + BL/2
3 + BL/2
3
3.5
2
1
2
10
200
1
1
1
Data Sheet E0089H40 (Ver. 4.0)
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