HB54A5129F1U-B75B Datasheet, PDF (13/16 Pages) Elpida Memory – 512MB Registered DDR SDRAM DIMM

HB54A5129F1U-B75B/10B
Pin Capacitance (TA = 25°C, VCC, VCCQ = 2.5V ± 0.2V)
Parameter
Symbol
Pins
max.
Unit
Notes
Input capacitance
CI1
Address, /RAS, /CAS, /WE,
/S, CKE
10
pF
1, 3
Input capacitance
CI2
CK, /CK
20
pF
1, 3
Data and DQS input/output
capacitance
CO
DQ, DQS, CB
15
pF
1, 2, 3
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VCCQ/2, ∆VOUT = 0.2V.
2. Dout circuits are disabled.
3. This parameter is sampled and not 100% tested.
Timing Parameter Measured in Clock Cycle for Registered DIMM
E_Parameter
Write to pre-charge command delay (same bank)
O^{Read to pre-charge command delay (same bank)}
Write to read command delay (to input all data)
Burst stop command to write command delay
(CL = 3)
L ^{(CL = 3.5)}
Symbol
tWPD
tRPD
tWRD
tBSTW
tBSTW
Number of clock cycle
min.
max.
3 + BL/2
BL/2
2 + BL/2
2
3
Unit.
tCK
tCK
tCK
tCK
tCK
Burst stop command to DQ High-Z
(CL = 3)
tBSTZ
3
tCK
(CL = 3.5)
tBSTZ
3.5
tCK
Read command to write command delay (to output all data)
(CL = 3)
tRWD
2 + BL/2
tCK
(CL = 3.5)
tRWD
3 + BL/2
tCK
P _{Pre-charge command to High-Z}
(CL = 3)
tHZP
3
tCK
(CL = 3.5)
tHZP
3.5
tCK
Write command to data in latency
tWCD
2
tCK
r _{Write recovery}
tWR
1
tCK
Register set command to active or register set command
tMRD
2
tCK
o _{Self refresh exit to non-read command}
tSNR
10
tCK
Self refresh exit to read command
tSRD
200
tCK
Power down entry
tPDEN
1
tCK
d ^{Power down exit to command input}
tPDEX
1
tCK
uct ^{CKE minimum pulse width}
tCKEPW
1
tCK
Data Sheet E0191H40 (Ver. 4.0)
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