EDJ1108BDBG Datasheet, PDF (122/147 Pages) Elpida Memory – 1G bits DDR3 SDRAM

EDJ1108BDBG
Power-Down Mode
Power-down is synchronously entered when CKE is registered low (along with NOP or DESL command). CKE is not
allowed to go low while mode register set command, MPR operations, ZQCAL operations, DLL locking or read/write
operation are in progress. CKE is allowed to go low while any of other operations such as row activation, precharge
or auto precharge and refresh are in progress, but power-down IDD spec will not be applied until finishing those
operations.
The DLL should be in a locked state when power-down is entered for fastest power-down exit timing. If the DLL is
not locked during power-down entry, the DLL must be reset after exiting power-down mode for proper read operation
and synchronous ODT operation. DRAM design provides all AC and DC timing and voltage specification as well
proper DLL operation with any CKE intensive operations as long as DRAM controller complies with DRAM
specifications.
During power-down, if all banks are closed after any in-progress commands are completed, the device will be in
precharge power-down mode; if any bank is open after in-progress commands are completed, the device will be in
active power-down mode.
Entering power-down deactivates the input and output buffers, excluding CK, /CK, ODT, CKE and /RESET. To
protect DRAM internal delay on CKE line to block the input signals, multiple NOP or DESL commands are needed
during the CKE switch off and cycle(s) after this timing period are defined as tCPDED. CKE_low will result in
deactivation of command and address receivers after tCPDED has expired.
[Power-Down Entry Definitions]
Status of DRAM
MR0 bit A12 DLL
PD Exit
Relevant Parameters
Active
(A bank
or
more
Open)
Don’t
Care
On
Precharged
(All banks Precharged)
0
Off
Precharged
(All Banks
1
On
Precharged)
Fast
Slow
Fast
tXP to any valid command
tXP to any valid command. Since it is in
precharge state, commands here will be
ACT, AR, MRS, PRE or PALL .
tXPDLL to commands who need DLL to
operate, such as READ, READA or ODT
control line.
tXP to any valid command
Also the DLL is disabled upon entering precharge power-down for slow exit mode, but the DLL is kept enabled
during precharge power-down for fast exit mode or active power-down. In power-down mode, CKE low, RESET high
and a stable clock signal must be maintained at the inputs of the DDR3 SDRAM, and ODT should be in a valid state
but all other input signals are “Don’t Care” (If RESET goes low during power-down, the DRAM will be out of PD
mode and into reset state). CKE low must be maintained until tPD has been satisfied. Power-down duration is
limited by 9 times tREFI of the device.
The power-down state is synchronously exited when CKE is registered high (along with a NOP or DESL command).
CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with
power-down exit latency, tXP and/or tXPDLL after CKE goes high. Power-down exit latency is defined at AC
Characteristics table of this data sheet.
Data Sheet E1544E30 (Ver. 3.0)
122