EDD2508AKTA-LI Datasheet, PDF (12/49 Pages) Elpida Memory – 256M bits DDR SDRAM WTR (Wide Temperature Range)

EDD2508AKTA-LI
CKE (input pin)
This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is
Low. CKE controls power down and self-refresh. The power down and the self-refresh commands are entered
when the CKE is driven Low and exited when it resumes to High. CKE must be maintained high throughout read or
write access.
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge
and the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper
hold time tIH.
DM (input pin)
DM is the reference signal of the data input mask function. DM is sampled at the cross point of DQS and VREF.
DQ0 to DQ7 (input/output pins)
EData is input to and output from these pins.
DQS (input and output pin)
DQS provides the read data strobe (as output) and the write data strobe (as input).
O_{VDD, VSS, VDDQ, VSSQ (Power supply)}
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
L ^buffers.
Product
Preliminary Data Sheet E0434E10 (Ver. 1.0)
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