EBD25EC8AKFA-5 Datasheet, PDF (12/19 Pages) Elpida Memory – 256MB Unbuffered DDR SDRAM DIMM (32M words X72 bits, 1 Rank)

EBD25EC8AKFA-5
Pin Capacitance (TA = 25°C, VDD = 2.6V ± 0.1V)
Parameter
Input capacitance
Input capacitance
Data and DQS input/output
capacitance
Symbol
CI1
CI2
CO
Pins
max.
Address, /RAS, /CAS, /WE,
/CS, CKE
73
CK, /CK
50
DQ, CB, DQS, DM
10
Unit
Notes
pF
pF
pF
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.6V ± 0.1V, VSS = 0V)
(DDR SDRAM Component Specification)
-5B
-5C
Parameter
Clock cycle time
CK high-level width
CK low-level width
Symbol
tCK
tCH
tCL
CK half period
tHP
DQ output access time from CK, /CK
DQS output access time from CK, /CK
DQS to DQ skew
DQ/DQS output hold time from DQS
Data hold skew factor
Data-out high-impedance time
from CK, /CK
Data-out low-impedance time
from CK, /CK
Read preamble
Read postamble
DQ and DM input setup time
DQ and DM input hold time
DQ and DM input pulse width
Write preamble setup time
Write preamble
Write postamble
Write command to first DQS latching
transition
DQS falling edge to CK setup time
DQS falling edge hold time from CK
DQS input high pulse width
DQS input low pulse width
Address and control input setup time
Address and control input hold time
Address and control input pulse width
Mode register set command cycle time
Active to Precharge command period
Active to Active/Auto refresh command
period
tAC
tDQSCK
tDQSQ
tQH
tQHS
tHZ
tLZ
tRPRE
tRPST
tDS
tDH
tDIPW
tWPRES
tWPRE
tWPST
tDQSS
tDSS
tDSH
tDQSH
tDQSL
tIS
tIH
tIPW
tMRD
tRAS
tRC
min.
max.
5
8
0.45
0.55
0.45
0.55
min
(tCH, tCL)
—
–0.7
0.7
–0.55
0.55
—
0.4
tHP – tQHS —
—
0.5
—
0.7
–0.7
0.7
0.9
1.1
0.4
0.6
0.4
—
0.4
—
1.75
—
0
—
0.25
—
0.4
0.6
0.72
1.28
0.2
—
0.2
—
0.35
—
0.35
—
0.6
—
0.6
—
2.2
—
2
—
40
120000
55
—
min.
max.
5
8
0.45
0.55
0.45
0.55
min
(tCH, tCL)
—
–0.7
0.7
–0.55
0.55
—
0.4
tHP – tQHS —
—
0.5
—
0.7
–0.7
0.7
0.9
1.1
0.4
0.6
0.4
—
0.4
—
1.75
—
0
—
0.25
—
0.4
0.6
0.72
1.28
0.2
—
0.2
—
0.35
—
0.35
—
0.6
—
0.6
—
2.2
—
2
—
40
120000
60
—
Unit Notes
ns 10
tCK
tCK
tCK
ns 2, 11
ns
2, 11
ns 3
ns
ns
ns
5, 11
ns 6, 11
tCK
tCK
ns 8
ns 8
ns 7
ns
tCK
tCK 9
tCK
tCK
tCK
tCK
tCK
ns 8
ns 8
ns 7
tCK
ns
ns
Preliminary Data Sheet E0354E30 (Ver. 3.0)
12