EDJ1108BABG Datasheet, PDF (114/148 Pages) Elpida Memory – 1G bits DDR3 SDRAM

EDJ1108BABG, EDJ1116BABG
CK
/CK
Command*³
Address*⁴
DQS, /DQS
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14
WRIT
Bank
Col n
NOP
tBL = 4 clocks
tWPRE
tWPST
tWTR
READ NOP
Bank
Col b
DQ*²
WL = 5
Din Din Din Din
n n+1 n+2 n+3
RL = 5
Notes: 1. BC4, RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. Din n = data-in from column n; Dout b = data-out from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T0.
READ command at T13 can be either BC4 or BL8 depending on MR0 bit [A1, A0] and A12 status at T13.
WRITE (BC4) to READ (BC4/BL8)
VIH or VIL
CK
/CK
Command*³
Address*⁴
DQS, /DQS
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14
WRIT
Bank
Col n
NOP
tCCD
WRIT
Bank
Col b
tWPRE
NOP
tBL = 4 clocks
tWPST
tWR
tWTR
DQ*²
WL = 5
Din Din Din Din Din Din Din Din Din Din Din Din
n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3
WL = 5
Notes: 1. WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0.
BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T4.
WRITE (BL8) to WRITE (BC4)
VIH or VIL
Data Sheet E1248E40 (Ver. 4.0)
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