EBE51UD8AEFA Datasheet, PDF (11/22 Pages) Elpida Memory – 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)

EBE51UD8AEFA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
Parameter
Operating current
(ACT-PRE)
Symbol Grade
IDD0
-5C
-4A
Operating current
-5C
IDD1
(ACT-READ-PRE)
-4A
Precharge power-down
standby current
IDD2P
-5C
-4A
Precharge quiet standby
current
IDD2Q
-5C
-4A
-5C
Idle standby current
IDD2N
-4A
Active power-down
standby current
-5C
IDD3P-F _-4A
IDD3P-S ^-5C
-4A
-5C
Active standby current IDD3N
-4A
Operating current
(Burst read operating)
IDD4R
-5C
-4A
Operating current
-5C
(Burst write operating) ^IDD4W
-4A
max.
880
760
1000
880
80
64
200
160
240
200
320
280
200
160
520
480
1520
1200
1520
1200
Unit Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
mA CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
mA tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA CKE is H, /CS is H;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open;
mA tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and address bus
mA
inputs are STABLE;
Slow PDN Exit
Data bus inputs are FLOATING ^{MRS(12) = 1}
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
mA CKE is H, /CS is H between valid commands;
Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
mA
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
mA
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Data Sheet E0584E30 (Ver. 3.0)
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