EBE21RD4AGFB Datasheet, PDF (11/23 Pages) Elpida Memory – 2GB Registered DDR2 SDRAM DIMM

EBE21RD4AGFB
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
Parameter
Operating current
(ACT-PRE)
Symbol Grade
-6E
IDD0 -5C
-4A
max
3970
3660
3250
Operating current
(ACT-READ-PRE)
-6E
IDD1 -5C
-4A
4320
3980
3560
Precharge power-down
standby current
-6E
IDD2P -5C
-4A
Precharge quiet standby
current
-6E
IDD2Q -5C
-4A
Idle standby current
Active power-down
standby current
-6E
IDD2N -5C
-4A
-6E
IDD3P-F -5C
-4A
-6E
IDD3P-S -5C
-4A
Active standby current
-6E
IDD3N -5C
-4A
970
930
810
1510
1470
1250
1870
1650
1430
2050
2010
1790
1510
1470
1250
3160
2940
2710
Operating current
(Burst read operating)
-6E
IDD4R -5C
-4A
5620
4830
4140
Operating current
(Burst write operating)
-6E
IDD4W -5C
-4A
5440
4830
4140
Unit
Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
mA
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
mA
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA
CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA
CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA
CKE is H, /CS is H;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
all banks open;
tCK = tCK (IDD);
mA
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and
address bus inputs are
mA
STABLE;
Data bus inputs are
Slow PDN Exit
MRS(12) = 1
FLOATING
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
tRP = tRP (IDD);
mA
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA
tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA
tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Preliminary Data Sheet E0898E10 (Ver. 1.0)
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