EBE10RD4AEFA Datasheet, PDF (11/22 Pages) Elpida Memory – 1GB Registered DDR2 SDRAM DIMM (128M words x 72 bits, 1 Rank)

EBE10RD4AEFA
DC Characteristics 1 (TC = 0°C to +85°C, VDD = 1.8V ± 0.1V, VSS = 0V)
Parameter
Operating current
(ACT-PRE)
Symbol Grade
-5C
IDD0
-4A
max.
2440
2120
Operating current
(ACT-READ-PRE)
-5C
IDD1
-4A
2760
2430
Precharge power-down
standby current
-5C
IDD2P
-4A
Precharge quiet standby
current
-5C
IDD2Q
-4A
Idle standby current
-5C
IDD2N
-4A
-5C
IDD3P-F
-4A
Active power-down standby
current
-5C
IDD3P-S
-4A
Active standby current
-5C
IDD3N
-4A
700
620
970
840
1060
930
1240
1110
970
840
1720
1580
Operating current
(Burst read operating)
-5C
IDD4R
-4A
3660
3060
Operating current
(Burst write operating)
-5C
IDD4W
-4A
3660
3060
Unit
Test condition
one bank; tCK = tCK (IDD), tRC = tRC (IDD),
tRAS = tRAS min.(IDD);
mA
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
one bank; IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRC = tRC (IDD),
mA
tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks idle;
tCK = tCK (IDD);
mA
CKE is L;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA
CKE is H, /CS is H;
Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
all banks idle;
tCK = tCK (IDD);
mA
CKE is H, /CS is H;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
all banks open;
mA
tCK = tCK (IDD);
CKE is L;
Fast PDN Exit
MRS(12) = 0
Other control and
address bus inputs are
mA
STABLE;
Data bus inputs are
Slow PDN Exit
MRS(12) = 1
FLOATING
all banks open;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
tRP = tRP (IDD);
mA
CKE is H, /CS is H between valid commands;
Other control and address bus inputs are
SWITCHING;
Data bus inputs are SWITCHING
all banks open, continuous burst reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP
mA
(IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
all banks open, continuous burst writes;
BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS max.(IDD),
mA
tRP = tRP (IDD);
CKE is H, /CS is H between valid commands;
Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Data Sheet E0644E30 (Ver. 3.0)
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