EBD26UC6AMSA Datasheet, PDF (11/19 Pages) Elpida Memory – 256MB DDR SDRAM SO-DIMM

EBD26UC6AMSA
DC Characteristics 1 (TA = 0 to 70°C, VDD = 2.5V ± 0.2V, VSS = 0V)
Parameter
Symbol
Grade
max.
Unit Test condition
Notes
Operating current (ACTV-PRE) IDD0
-6B
-7B
Operating current
(ACTV-READ-PRE)
IDD1
-6B
-7B
1040
960
1360
1240
mA
CKE ≥ VIH,
tRC = tRC (min.)
1, 2, 9
CKE ≥ VIH, BL = 4,
mA CL = 2.5,
1, 2, 5
tRC = tRC (min.)
Idle power down standby current IDD2P
64
mA CKE ≤ VIL
4
Floating idle standby current
Quiet idle standby current
Active power down
standby current
Active standby current
Operating current
(Burst read operation)
Operating current
(Burst write operation)
Auto refresh current
Self refresh current
Operating current
(4 banks interleaving)
IDD2F
-6B
-7B
IDD2Q
-6B
-7B
IDD3P
-6B
-7B
IDD3N
-6B
-7B
IDD4R
-6B
-7B
IDD4W
-6B
-7B
IDD5
-6B
-7B
IDD6
IDD7A
-6B
-7B
560
480
560
480
400
320
720
640
2360
1760
1960
1600
2320
2240
48
3000
2720
mA
CKE ≥ VIH, /CS ≥ VIH,
DQ, DQS, DM = VREF
4, 5
mA
CKE ≥ VIH, /CS ≥ VIH,
DQ, DQS, DM = VREF
4, 10
mA CKE ≤ VIL
3
mA
CKE ≥ VIH, /CS ≥ VIH
tRAS = tRAS (max.)
3, 5, 6
mA
CKE ≥ VIH, BL = 2,
CL = 2.5
1, 2, 5, 6
mA
CKE ≥ VIH, BL = 2,
CL = 2.5
1, 2, 5, 6
mA
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
mA
Input ≥ VDD – 0.2 V
Input ≤ 0.2 V
mA BL = 4
1, 5, 6, 7
Notes. 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one cycle.
6. DQ, DM, DQS transition twice per one cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycles.
10. Command/Address stable at ≥ VIH or ≤ VIL.
DC Characteristics 2 (TA = 0 to 70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
Parameter
Symbol
min.
max.
Unit
Test condition
Input leakage current
ILI
–16
16
Output leakage current
ILO
–10
10
Output high current
IOH
–16.2
—
Output low current
IOL
16.2
—
Note: 1. DDR SDRAM component specification.
µA
VDD ≥ VIN ≥ VSS
µA
VDD ≥ VOUT ≥ VSS
mA
VOUT = 1.95V
mA
VOUT = 0.35V
Note
1
1
Preliminary Data Sheet E0499E10 (Ver. 1.0)
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