EDJ5316DBBG Datasheet, PDF (104/173 Pages) Elpida Memory – 512M bits DDR3 SDRAM

EDJ5316DBBG
CK
/CK
Command*³
Address*⁴
DQS, /DQS
T0
T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14
READ
Bank
Col n
NOP
tCCD
READ
Bank
Col b
tRPRE
NOP
tRPST
tRPRE
tRPST
DQ*²
RL = 5
Dout Dout Dout Dout
n n+1 n+2 n+3
RL = 5
Dout Dout Dout Dout Dout Dout Dout Dout
b b+1 b+2 b+3 b+4 b+5 b+6 b+7
Notes: 1. RL = 5 (CL = 5, AL = 0).
2. Dout n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0.
BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T4.
VIH or VIL
CK
/CK
Command*³
Address*⁴
DQS, /DQS
READ (BC4) to READ (BL8) OTF
T0
T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
READ
NOP
WRIT
READ to WRIT command delay = RL + tCCD/2 + 2tCK − WL
Bank
Col n
Bank
Col b
tRPRE
tRPST
tWPRE
NOP
tBL = 4 clocks
tWR
tWTR
tWPST
DQ*²
RL = 5
Dout Dout Dout Dout
n n+1 n+2 n+3
WL = 5
Din Din Din Din Din Din Din Din
b b+1 b+2 b+3 b+4 b+5 b+6 b+7
Notes: 1. RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0).
2. Dout n = data-out from column n , Din b= data-in from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0.
BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T4.
READ (BC4) to WRITE (BL8) OTF
VIH or VIL
Preliminary Data Sheet E1462E30 (Ver. 3.0)
104