HB52RF1289E2-75B Datasheet, PDF (10/16 Pages) Elpida Memory – 1 GB Registered SDRAM DIMM 128-Mword × 72-bit, 133 MHz Memory Bus, 2-Bank Module (36 pcs of 64 M × 4 Components) PC133 SDRAM

HB52RF1289E2-75B
DC Characteristics (Ta = 0 to 55°C, V_CC = 3.3 V ± 0.3 V, V_SS = 0 V)
HB52RF1289E2-75B
Parameter
Symbol Min
Max
Unit Test conditions Notes
Operating current
I _CC1
—
Standby current in power I_CC2P
—
down
3215
803
Burst length = 1 1, 2, 3
mA
t_RC = min
mA
CKE = V_IL, t_CK = 12 6
ns
Standby current in power I_CC2PS
—
down (input signal stable)
767
mA
CKE = V_IL, t_CK = ∞ 7
Standby current in non I_CC2N
—
power down
Active standby current in I_CC3P
—
power down
1415
839
mA
CKE, S = V_IH,
4
t_CK = 12 ns
mA
CKE = V_IL, t_CK = 12 1, 2, 6
ns
Active standby current in I_CC3N
—
non power down
Burst operating current
I _CC4
—
Refresh current
I _CC5
—
Self refresh current
I _CC6
—
Input leakage current
I _LI
–10
Output leakage current I_LO
–10
1775
3575
5195
803
10
10
mA
CKE, S = V_IH,
t_CK = 12 ns
1, 2, 4
t_CK = min, BL = 4 1, 2, 5
mA
t_RC = min
3
mA
mA
V_IH ≥ V_CC – 0.2 V
8
V_IL ≤ 0.2 V
µA
0 ≤ Vin ≤ V_CC
µA
0 ≤ Vout ≤ V_CC
DQ = disable
Output high voltage
V_OH
2.4
—
V
I_OH = –4 mA
Output low voltage
V_OL
—
0.4
V
I_OL = 4 mA
Notes: 1. I_CC depends on output load condition when the device is selected. I_CC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK operating current.
7. After power down mode, no CK operating current.
8. After self refresh mode set, self refresh current.
Data Sheet E0018H10
10