EDS6416GHTA Datasheet, PDF (1/49 Pages) Elpida Memory – 64M bits SDRAM

DATA SHEET
64M bits SDRAM
EDS6416GHTA (4M words × 16 bits) _{Specifications}
• Density: 64M bits
• Organization
⎯ 1M words × 16 bits × 4 banks
E• Package: 54-pin plastic TSOP (II)
⎯ Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 3.3V ± 0.3V
• Clock frequency: 108MHz/CL2
O^100MHz/CL3
• Four internal banks for concurrent operation
• Interface: LVTTL
• Burst lengths (BL): 1, 2, 4, 8, full page
L ^{• Burst type (BT):}
Pin Configurations
/xxx indicates active low signal.
54-pin Plastic TSOP (II)
VDD ¹
54
DQ0 ²
53
VDDQ
3
52
DQ1 ⁴
51
DQ2 ⁵
50
VSSQ
6
49
DQ3 ⁷
48
DQ4 ⁸
47
VDDQ
9
46
DQ5 ¹⁰
45
DQ6 ¹¹
44
VSSQ
12
43
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
⎯ Sequential (1, 2, 4, 8, full page)
⎯ Interleave (1, 2, 4, 8)
• /CAS Latency (CL): 2, 3
• Precharge: auto precharge operation for each burst
access
• Refresh: auto-refresh, self-refresh
P _{• Refresh cycles: 4096 cycles/64ms}
⎯ Average refresh period: 15.6μs
• Operating ambient temperature range
⎯ TA = 0°C to +70°C
r _Features
o ^{• Single pulsed /RAS}
• Burst read/write operation and burst read/single write
operation capability
• Byte control by UDQM and LDQM
duct • tDPL = 1CLK
DQ7 ¹³
VDD ¹⁴
LDQM ¹⁵
/WE ¹⁶
/CAS ¹⁷
/RAS ¹⁸
/CS ¹⁹
BA0 ²⁰
BA1 ²¹
A10 ²²
A0 ²³
A1 ²⁴
A2 ²⁵
A3 ²⁶
VDD ²⁷
42 _DQ8
41 _VSS
40 _NC
39 _UDQM
38 _CLK
37 _CKE
36 _NC
35 _A11
34 _A9
33 _A8
32 _A7
31 _A6
30 _A5
29 _A4
28 _VSS
(Top view)
A0 to A11
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
LDQM, UDQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
NC
No connection
Document No. E0498E30 (Ver. 3.0)
Date Published December 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
This product became EOL in April, 2007.
©Elpida Memory, Inc. 2004-2005