EDS6416AHTA Datasheet, PDF (1/49 Pages) Elpida Memory – 64M bits SDRAM (4M words x 16 bits)

DATA SHEET
64M bits SDRAM
EDS6416AHTA, EDS6416CHTA
(4M words × 16 bits)
Description
Pin Configurations
The EDS6416AHTA, EDS6416CHTA are 64M bits
SDRAMs organized as 1,048,576 words × 16 bits × 4
banks. All inputs and outputs are synchronized with
the positive edge of the clock.
Supply voltages are 3.3V (EDS6416AHTA) and 2.5V
(EDS6416CHTA).
It is packaged in 54-pin plastic TSOP (II).
Features
• 3.3V and 2.5V power supply
• Clock frequency: 166MHz/133MHz (max.)
• Single pulsed /RAS
• ×16 organization
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single
write operation capability
• 2 variations of burst sequence
 Sequential (BL = 1, 2, 4, 8, full page)
 Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by UDQM and LDQM
• Refresh cycles: 4096 refresh cycles/64ms
• 2 variations of refresh
 Auto refresh
 Self refresh
• TSOP (II) package with lead free solder (Sn-Bi)
 RoHS compliant
/xxx indicate active low signal.
54-pin Plastic TSOP (II)
VDD ¹
54
DQ0 ²
53
VDDQ
3
52
DQ1 ⁴
51
DQ2 ⁵
50
VSSQ
6
49
DQ3 ⁷
48
DQ4 ⁸
47
VDDQ
9
46
DQ5 ¹⁰
45
DQ6 ¹¹
44
VSSQ
12
43
DQ7 ¹³
42
VDD ¹⁴
41
LDQM ¹⁵
40
/WE ¹⁶
39
/CAS ¹⁷
38
/RAS ¹⁸
37
/CS ¹⁹
36
BA0 ²⁰
35
BA1 ²¹
34
A10 ²²
33
A0 ²³
32
A1 ²⁴
31
A2 ²⁵
30
A3 ²⁶
29
VDD ²⁷
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
(Top view)
A0 to A11
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
LDQM, UDQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0439E60 (Ver.6.0)
Date Published June 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2003-2005