EDS2516JEBH-75R3 Datasheet, PDF (1/50 Pages) Elpida Memory – 256M bits AS SDRAM

PRELIMINARY DATA SHEET
256M bits AS SDRAM
EDS2516JEBH-75R3 (16M words × 16 bits) _Description
The EDS2516JEBH-75R3 is a 256M bits AS SDRAM
(Application Specific SDRAM) organized as 4,194,304
words × 16 bits × 4 banks and specified suitable for
portable digital consumer electronics.
EIt is packaged in 54-ball FBGA.
Features
• 2.5V power supply
O_{• Clock frequency: 133MHz (max.)}
• LVCMOS interface
• Single pulsed /RAS
• ×16 organization
• 4 banks can operate simultaneously and
L _{independently}
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8 and full
page
P ^{• 2 variations of burst sequence}
 Sequential (BL = 1, 2, 4, 8, full page)
 Interleave (BL = 1, 2, 4, 8)
• /CAS capability (CL): 3
r ^{• Programmable driver strength: Half , Quarter}
• Byte control by UDQM and LDQM
• Address
o _{ 8K Row address /512 column address}
• Refresh cycles
 8192 refresh cycles/16ms
d ^{• Auto refresh capability}
• FBGA package with lead free solder (Sn-Ag-Cu)
uct ^{ RoHS compliant}
Pin Configurations
/xxx indicate active low signal.
54-ball FBGA
123456789
A
VSS DQ15 VSSQ
VDDQ DQ0 VDD
B
DQ14 DQ13 VDDQ
VSSQ DQ2 DQ1
C
DQ12 DQ11 VSSQ
VDDQ DQ4 DQ3
D
DQ10 DQ9 VDDQ
VSSQ DQ6 DQ5
E
DQ8 NC VSS
VDD LDQM DQ7
F
UDQM CLK CKE
/CAS /RAS /WE
G
A12 A11 A9
BA0 BA1 /CS
H
A8 A7 A6
A0 A1 A10
J
VSS A5 A4
A3 A2 VDD
(Top view)
A0 to A12
BA0, BA1
DQ0 to DQ15
/CS
/RAS
/CAS
/WE
LDQM /UDQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data input/ output
Chip select
Row address strobe
Column address strobe
Write enable
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0811E10 (Ver. 1.0) _{This product became EOL in October, 2007.}
Date Published September 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005