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EDS2516APTA Datasheet, PDF (1/53 Pages) Elpida Memory – 256M bits SDRAM
DATA SHEET
256M bits SDRAM
EDS2516APTA (16M words × 16 bits) Description
The EDS2516AP is a 256M bits SDRAM organized as
4,194,304 words × 16 bits × 4 banks. All inputs and
outputs are referred to the rising edge of the clock
Einput. It is packaged in standard 54-pin plastic TSOP
(II)
Features
• 3.3V power supply
O• Clock frequency: 166MHz/133MHz (max.)
• LVTTL interface
• Single pulsed /RAS
• ×16 organization
L • 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8, full page
• 2 variations of burst sequence
P ⎯ Sequential (BL = 1, 2, 4, 8, full page)
⎯ Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by UDQM and LDQM
r Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
⎯ Auto refresh
o ⎯ Self refresh
• 2 types of TSOP (II) package
⎯ Sn-Pb solder
duct ⎯ Lead free solder (Sn-Bi)
Pin Configurations
/xxx indicates active low signal.
54-pin plastic TSOP (II)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10
A0
A1
A2
A3
VDD
1
54
2
53
3
52
4
51
5
50
6
49
7
48
8
47
9
46
10
45
11
44
12
43
13
42
14
41
15
40
16
39
17
38
18
37
19
36
20
35
21
34
22
33
23
32
24
31
25
30
26
29
27
28
(Top view)
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
A0 to A12, Address input
BA0, BA1 Bank select address
DQ0 to DQ15 Data-input/output
/CS
Chip select
/RAS
Row address strobe
/CAS
Column address strobe
/WE
Write enable
UDQM,LDQM Input/output mask
CKE
Clock enable
CLK
Clock input
VDD
Power for internal circuit
VSS
Ground for internal circuit
VDDQ
Power for DQ circuit
VSSQ
Ground for DQ circuit
NC
No connection
Document No. E0359E20 (Ver. 2.0)
Date Published January 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
This product became EOL in March, 2007.
©Elpida Memory, Inc. 2003-2005